A technique for coupling wiring patterns of upper layers and lower layers using vias is widely used for a printed board on which a semiconductor element, such as a large scale integration (LSI) chip, is mounted. When a plurality of vias for coupling signal lines of different layers are adjacent to one another in a printed board, noise may be caused by crosstalk among the adjacent vias, which is hereinafter referred to as crosstalk noise.
Particularly in recent years, as the communication speed or the processing speed of an electronic apparatus increases, the speed of signal transmission between an LSI chip and a printed board has been demanded to be higher while crosstalk has been easily caused among adjacent vias. Thus, the occurrence of the crosstalk noise have been suppressed typically by widening clearances among adjacent vias.
Japanese Laid-open Patent Publication No. 5-13649, Japanese Laid-open Patent Publication No. 10-270855, and Japanese Laid-open Patent Publication No. 2000-223841 are examples of related art.
The clearances among vias in a printed board are desired to correspond to the pitches of coupling terminals in LSI to be mounted. The pitches of coupling terminals in LSI have been narrowed every year because of the demand for the higher LSI density. Such a situation has made it more and more difficult to ensure sufficient clearances among vias so as to suppress the occurrence of crosstalk noise.
The present application is conceived in view of the above-described problem and is aimed at providing a printed board, a printed board unit, and a method of manufacturing the printed board, which may suppress the occurrence of crosstalk noise among vias even when the clearances among the vias are narrow.